We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based ...
CHIPS Alliance has developed an open-source riscv-dv random instruction generator for RISC-V processor verification. This article focuses on the class riscv_asm_program_gen.sv and its various ...
CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software to be available through Intel Pathfinder for RISC-V ROCKVILLE, Md., Dec. 1, 2022 /PRNewswire/ -- CEVA, Inc. (NASDAQ: CEVA), the leading ...
Targeted, preconfigured RISC-V IP cores plus low-risk, easy-start, deferred-payment IP licensing make embedded RISC-V design easier than ever Santa Clara, California, RISC-V Summit — October 22, 2025 ...
It’s pretty neat to flash firmware on a microcontroller thousands of miles away and see the development board blink in response. We’ve covered the Open-V before, and the crowd funding campaign they ...
Early access program starts for PolarFire SoC, which delivers simultaneous support of real-time applications and rich operating systems with unparalleled power efficiency CHANDLER, Ariz., Dec. 10, ...
CAST, the semiconductor intellectual property provider, has unveiled the CAST Catalyst Program. This program is a new way for embedded system developers to adopt RISC-V processors faster and with less ...
The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
RISC-V is no longer content to disrupt the CPU industry. It is waging war against every type of processor integrated into an SoC or advanced package, an ambitious plan that will face stiff competition ...
READING, United Kingdom, May 28, 2025 /PRNewswire/ -- Aion Silicon (formerly Sondrel), a leading ASIC and SoC architecture partner, today announced it has secured a $12 million engagement to provide ...